1. Field of the Invention
The present invention relates to a semiconductor memory device having a source synchronous interface, and more particularly, to a semiconductor memory device having a low jitter source synchronous interface and a clocking method for reducing jitter.
2. Description of the Related Art
When data is transmitted between semiconductor devices, jitter restrains the transmission speed. To solve this problem, a source synchronous interface is used, which is generally referred to as forwarded clocking. A synchronous interface technique is disclosed in US 2002/0075980 A1.
FIG. 1 illustrates a conventional source synchronous interface method. Referring to FIG. 1, a transmitter TX 100 transmits a clock signal CLK along with data DATA to a receiver RX 110. In the transmitter 110, a circuit 11 transmitting the data DATA and a circuit 13 transmitting the clock signal CLK have the same configuration. A line transferring the data DATA and a line transferring the clock signal CLK are constructed in the same manner on a PCB.
The receiver 110 uses a phase locked loop (PLL) or a delay locked loop (DLL) 17 in order to perform a locking operation, generate a multi-phase clock signal and generate a high-frequency clock signal when receiving the clock signal CLK and generating an internal clock signal ICLK. A data receiving circuit 15 included in the receiver 100 receives the data DATA in response to the internal clock signal ICLK.
When the circuit illustrated in FIG. 1 is a memory system, the transmitter 100 corresponds to a memory controller and the receiver 110 corresponds to a memory device.
In the aforementioned source synchronous interface method, when jitter is applied to the line transferring the data DATA, similar jitter is applied to the line transferring the clock signal CLK. The influence of jitter is eliminated when the receiver 100 samples the data DATA using the received clock signal CLK. Accordingly, a data transfer rate may be increased.
When a PLL is used for a source synchronous interface, common mode jitter between data and a clock signal is removed only at frequencies lower than the bandwidth of the PLL although jitter of a clock signal having a high-frequency higher than the bandwidth of the PLL is eliminated. When a DLL is used for the source synchronous interface, the common mode jitter between the data and the clock signal is removed even at frequencies higher than the bandwidth of the DLL. However, a phase difference between the data and the clock signal may be generated due to a delay time of the DLL. This may cause jitter larger than the jitter generated when the PLL is used.
In other words, when a PLL is used at frequencies higher than a predetermined high frequency and a DLL is used at frequencies lower than the predetermined high frequency in the source synchronous interface, jitter between the data and the clock signal can be reduced at the receiver side.